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ARM known as Acorn RISC Machine basically established by British company ARM holdings. Acorn launched ARM in 1985 and built their first 26 bit ARM Processor and became commercial RISC processor in the world. Its construction used less than 25,000 transistors which was a small number at that time.
This first ARM architecture is now referred to as the ARM version 1 architecture. It was followed by the second processor in 1987. The main new feature introduced in ARM version 2 was coprocessor support. Later, the ARM v2 architecture was implemented with on-chip cache in the ARM3 processor.
ARM development board has multiple addressing modes, manual stack manipulation, reduced instruction set i.e.25, Most operations are executed over registers, all instructions can be conditional, Manual stack manipulation, Stack addressing must be explicitly programmed, Subroutines must be explicitly programmed, Big-endian and little-endian COMP-573A Microcomputers.
Most of the ARM’s use two instruction set – 32 bit ARM instruction set and second one is 16 bit thumb instruction set. ARM processor has seven basic operating modes which include user, FIQ, IRQ, supervisor, Abort, undef and system. Due to reduced instruction set, few transistors are used which makes architecture compact and simple.
Arm is the best extensively spread core processors and licensed in the world used particularly in portable devices. ARM is used because its cost efficient, lower power consumption, compact Size, using 8/16/32 bit microprocessor, using thumb mode, debug interface, multiplier and ICE interface. System on chip includes CPU Unit in which buffer, CPU core and cache is there. There also exit a memory interface, controller as per requirement, interrupt on controller, general purpose I/O with 37 registers. ARM Application is visible in smart phones, tables, multimedia players, mobile devices and wearing stuff.
ARM processor features include an orthogonal instruction set, load and store architecture set, for high performance 32 bit and 64 bit is used, provide hardware visualization support, having enhanced power saving design and having single cycle execution.
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